This invention relates to MFMOS one transistor memory structures and integrated processes for ferroelectric non-volatile memory devices and, more particularly, to MFMOS one transistor ferroelectric memory devices including high dielectric constant materials to reduce the operation voltage and to increase the memory window and reliability of the devices.
Many one transistor ferroelectric memory devices, such as MFMOS, MFOS and MFMS, have been proposed. However, no reliable memory devices have been fabricated because of the difficulty in selecting appropriate ferroelectric and dielectric materials, and due to the integrated process technology required for the one transistor memory devices. Due to the difficulty in forming a ferroelectric-semiconductor interface with good electrical properties, the MFMOSFET memory cell has been selected as a good candidate for fabrication.
The basic operational principles for a MFMOSFET memory device are depicted in FIGS. 1 and 2. Referring to FIG. 1, when the ferroelectric material is poled towards the gate electrode, a positive compensation charge is induced at the channel surface. Under these conditions, the transistor is in the xe2x80x9coffxe2x80x9d state (xe2x80x9c0xe2x80x9d state) and the threshold voltage (VT) is high. In contrast, referring to FIG. 2, when the ferroelectric material is poled towards the channel, a negative compensation charge is induced at the channel surface. Under these conditions, the transistor is in the xe2x80x9conxe2x80x9d state (xe2x80x9c1xe2x80x9d state) and the threshold voltage is low. During the read operation, a sense amplifier detects the state of the MFMOSFET device. If there is a current, it is assigned a xe2x80x9c1xe2x80x9d value; if there is no current, it is assigned a xe2x80x9c0xe2x80x9d value. This is the basic operational mechanism of a MFMOS one-transistor memory device.
For MFMOS one-transistor memory devices, the operation voltage, memory window, and reliability parameters such as retention, are critical issues. The operation voltage (VOP) for a MFMOS device is defined as VOP=VO+VF where VO and VF are the voltages applied on the oxide and the ferroelectric capacitor, respectively. In order to reduce the operation voltage and retain enough voltage to polarize the ferroelectric thin film, VO should be as small as possible. Due to the relationship VO=Qo/Co where QO and CO are the electrical charge and the capacitance of the oxide capacitor, respectively, decreasing the thickness or increasing the dielectric constant of the gate insulator thin film will reduce VO.
For a memory window, a plot of Log (ID) (Drain current) versus VG (Gate voltage) for a MFMOSFET device is depicted in FIGS. 3 and 4. In the xe2x80x9c0xe2x80x9d state the device is non-conductive while in the xe2x80x9c1xe2x80x9d state the device is conductive. The essential condition for an n-channel one transistor memory device is that the threshold voltage of the device in the xe2x80x9c0xe2x80x9d state should be larger than the operating voltage, and the threshold voltage of the device in the xe2x80x9c1xe2x80x9d state should be larger than 0.0 V. As shown in FIG. 3, if VT in the xe2x80x9c1xe2x80x9d state is negative, a high leakage current (ID) at VG=0 will be observed.
The memory window of a MFMOS device is equal to 2Pr/CFE, where, Pr and CFE are the remnant polarization and capacitance of the ferroelectric capacitor, respectively. According to a typical sheet carrier density in the channel region of a MOSFET device, a remnant polarization value larger than 0.2 xcexcC/cm2 of the ferroelectric thin film is enough for ferroelectric-gate FET applications. It is virtually impossible to maintain a positive threshold voltage in the xe2x80x9c1xe2x80x9d state if the remnant polarization is too high. The maximum induced charge of a Silicon Dioxide (SiO2) thin film is about 3.5 xcexcC/cm2 for an electric field of 10 MV/cm. The film breaks down at higher electrical fields. Therefore, in order to produce a reliable MFMOS device, one must select a ferroelectric material with a low dielectric constant, or increase the thickness of the ferroelectric thin film, which will result in a higher operation voltage.
Based on the mechanism of a MFMOS cell one-transistor memory device, the device will lose memory if depolarization occurs. Accordingly, the retention properties of the ferroelectric thin films are critical issues for one-transistor memory applications. The experimental results show that ferroelectric thin films with a saturated and square hysteresis loop and a large coercive field have excellent retention properties. However, a large coercive field also results in a higher operation voltage. In order make a reliable MFMOS one-transistor memory device, the ferroelectric thin film should have a saturated and square hysteresis loop, a low polarization value, a low dielectric constant, and an appropriate thickness and coercive field. For these reasons, ferroelectric Pb3Ge5O11 (PGO) with a low polarization (Pr) value and dielectric constant has been selected for one transistor memory applications. The experimental results show that PGO MFMOS capacitors with a 3.5 nm thick SiO2 layer exhibit high operation voltages. In order to reduce the operation voltage, one must either reduce the thickness of the SiO2 layer or select high dielectric constant materials. Reducing the thickness of the SiO2 layer has its limitations. Accordingly, there is a need for a high dielectric constant material for use in PGO MFMOS structure one transistor memory devices.
The assembly of the present invention provides a high dielectric constant material for MFMOS structure one transistor memory applications to reduce the operation voltage, and to increase the memory window and reliability of the device. In the preferred embodiments, the ferroelectric material comprises PGO and the high dielectric material comprises ZrO2, Y2O3, HfO2, La2O3, or the like, or mixtures thereof.
Accordingly, an object of the invention is to provide a reliable MFMOS device.
Another object of the invention is to provide a MFMOS device having a high dielectric material in order to reduce the operation voltage of the device.
A further object of the invention is to provide a MFMOS one transistor memory device wherein the ferroelectric thin film has a saturated and square hysteresis loop, a low polarization value, a low dielectric constant, and an appropriate thickness and coercive field.